general description the ds1805 addressable digital potentiometer contains a single 256-position digitally controlled potentiometer. device control is achieved through a 2-wire serial inter- face. device addressing is provided through three address inputs that allow up to eight devices on a sin- gle 2-wire bus. the exact wiper position of the poten- tiometer can be written or read. the ds1805 is available in 16-pin so and 14-pin tssop packages. the device is available in three standard resistance val- ues: 10k ? , 50k ? , and 100k ? . the ds1805 is specified over the industrial temperature range. the ds1805 provides a low-cost alternative for designs based on the ds1803, but require only a single potentiometer. applications ccfl inverters pdas and cell phones portable electronics multimedia products instrumentation and industrial controls features ? 3v or 5v operation ? low power consumption ? one digitally controlled, 256-position potentiometer ? compatible with ds1803-based designs ? 14-pin tssop (173mil) and 16-pin so (150mil) available for surface-mount applications ? three address inputs ? serial 2-wire bus ? operating temperature range industrial: -40? to +85? ? standard resistance values ds1805-010: 10k ? ds1805-050*: 50k ? ds1805-100*: 100k ? ds1805 addressable digital potentiometer ______________________________________________ maxim integrated products 1 14 13 12 11 10 9 8 1 2 3 4 5 6 7 v cc n.c. n.c. n.c. a2 w1 l1 h1 top view n.c. sda scl gnd a0 a1 14 tssop (173mil) ds1805e 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 h1 v cc n.c. n.c. n.c. n.c. n.c. sda scl 16 so (150mil) n.c. l1 a1 w1 a2 a0 gnd ds1805z pin configurations ordering information p art tem p ra nge pin- pac kage r esistance ( k ? ) ds 1805e-010 - 40 c to +85 c 14 tssop (173mil) 10 ds 1805e-050* - 40 c to +85 c 14 tssop (173mil) 50 ds 1805e-100* - 40 c to +85 c 14 tssop (173mil) 100 ds 1805z-010 - 40 c to +85 c 16 so (150mil) 10 ds 1805z-050* - 40 c to +85 c 16 so (150mil) 50 ds 1805z-100* - 40 c to +85 c 16 so (150mil) 100 xx-xxxx; rev 0; 4/02 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. add ?t&r?for tape-and-reel orders. *future product.
ds1805 addressable digital potentiometer 2 _____________________________________________________________________ absolute maximum ratings recommended dc operating conditions (t a = -40? to +85?) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage on any pin relative to ground .................-0.5v to +6.0v operating temperature range ...........................-40? to +85? storage temperature range .............................-55? to +125? soldering temperature............................................see ipc/jedec j-std-020a specification parameter symbol conditions min typ max units supply voltage v cc (note 1) 2.7 5.5 v resistor inputs l, h, w (note 1) -0.3 v cc + 0.3 v dc electrical characteristics (v cc = 2.7v to 5.5v, t a = -40? to +85?.) parameter symbol conditions min typ max units supply current active i cc (note 2) 200 ? input leakage i il -1 +1 ? wiper resistance r w 400 1000 ? wiper current i w 1ma input logic 1 v ih 0.7v cc v cc + 0.3 v input logic 0 v il gnd - 0.3 0.3v cc v input logic 1 0.7v cc v cc + 0.3 input logic levels a0, a1, a2 (note 3) input logic 0 gnd - 0.3 0 . 2 5 v c c v input current each i/o pin (note 4) 0.4v < v i/o < 0.9v cc -10 +10 ? standby current i stby (note 5) 20 40 ? v ol1 3ma sink current 0 0.4 v low-level output voltage v ol2 6ma sink current 0 0.6 v i/o capacitance c i/0 10 pf pulse width of spikes that must be suppressed by the input filter t sp fast mode 0 50 ns
ds1805 addressable digital potentiometer _____________________________________________________________________ 3 analog resistor characteristics (v cc = 2.7v to 5.5v, t a = -40? to +85?) parameter symbol conditions min typ max units end-to-end resistor tolerance (note 6) -20 +20 % absolute linearity (note 7) -0.75 +0.75 lsb relative linearity (note 8) -0.3 +0.3 lsb -3db cutoff frequency f cutoff (note 9) hz ratiometric temperature coefficient 8 ppm/? end-to-end temperature coefficient 550 ppm/? capacitance c i 5pf ac electrical characteristics (v cc = 2.7v to 5.5v, t a = -40? to +85?) parameter symbol conditions min typ max units fast mode 0 400 scl clock frequency (note 10) f scl standard mode 0 100 khz fast mode 1.3 bus free time between stop and start condition (note 10) t buf standard mode 4.7 ? fast mode 0.6 hold time (repeated) start condition (notes 10, 11) t hd:sta standard mode 4.0 ? fast mode 1.3 low period of scl clock (note 10) t low standard mode 4.7 ? fast mode 0.6 high period of scl clock (note 10) t high standard mode 4.0 ? fast mode 0 0.9 data hold time (notes 10, 12, 13) t hd:dat standard mode 0 0.9 ? fast mode 100 data setup time (note 10) t su:dat standard mode 250 ns fast mode 20 + 0.1c b 300 rise time of both sda and scl signals (notes 10, 14) t r standard mode 20 + 0.1c b 1000 ns fast mode 20 + 0.1c b 300 fall time of both sda and scl signals (notes 10, 14) t f standard mode 20 + 0.1c b 300 ns fast mode 0.6 setup time for stop condition (note 10) t su:sto standard mode 4.0 ? capacitive load for each bus line (note 14) c b 400 pf
ds1805 addressable digital potentiometer 4 _____________________________________________________________________ note 1: all voltages are referenced to ground. note 2: i cc specified with sda pin open. scl = 400khz clock rate. note 3: address inputs a0, a1, and a2 should be connected to either v cc or gnd, depending on the desired address selections. note 4: i/o pins of fast mode devices must not obstruct the sda and scl lines if v cc is switched off. note 5: i stby specified with sda = scl = v cc = 5.0v. note 6: valid at +25 c only. note 7: absolute linearity is used to determine wiper voltage versus expected voltage as determined by wiper position. note 8: relative linearity is used to determine the change in voltage between successive tap positions. note 9: -3db cutoff frequency characteristics for the ds1805 depend on potentiometer total resistance: ds1805-010, 1mhz; ds1805-50, 200khz; ds1805-100, 100khz. note 10: a fast mode device can be used in a standard mode system, but the requirement t su:dat > 250ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su:dat = 1000ns + 250ns = 1250ns before the scl line is released. note 11: after this period, the first clock pulse is generated. note 12: the maximum t hd:dat has only to be met if the device does not stretch the low period (t low ) of the scl signal. note 13: a device must internally provide a hold time of at least 300ns for the sda signal (referred to the v ihmin of the scl signal) in order to bridge the undefined region of the falling edge of scl. note 14: c b ?otal capacitance of one bus line in picofarads, timing referenced to (0.9)(v cc ) and (0.1)(v cc ). ac electrical characteristics (v cc = 2.7v to 5.5v, t a = -40? to +85?)
t ypical operating characteristics (v cc = 5.0v, t a = +25 c, unless otherwise noted.) ds1805 addressable digital potentiometer _____________________________________________________________________ 5 voltage-divider absolute linearity vs. wiper setting (10k ? ) ds1805 toc07 wiper setting absolute linearity (lsb) 200 150 50 100 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0 0.02 0 250 voltage-divider relative linearity vs. wiper setting (10k ? ) ds1805 toc08 wiper setting relative linearity (lsb) 200 150 100 50 0 0.01 0.02 0.03 0.04 0.05 0.06 -0.01 0 250 active supply current vs. scl frequency ds1805 toc06 scl frequency (khz) active supply current ( a) 300 200 100 5 10 15 20 25 30 35 40 45 50 0 0 400 sda = vcc a0, a1, a2, l1 = gnd w1, h1 = no connect end-to-end resistance temperature change vs. temperature ds1805 toc05 temperature ( c) end-to-end resistance % change 60 40 -20 0 20 -4 -3 -2 -1 0 1 2 3 4 5 -5 -40 80 tc = 530ppm/ c 10k ? , worst case voltage divider percent change (from +25 c) vs. temperature (ratiometric tc) ds1805 toc04 temperature ( c) % change (from +25 c) 60 40 20 0 -20 -0.04 -0.02 0 0.02 0.04 0.06 -0.06 -40 80 10k ? pot wiper = bfh wiper = bfh wiper = 3fh wiper = 3fh wiper = 7fh tc = 1.3ppm/ c tc = 8.1ppm/ c wiper resistance vs. wiper voltage (10k ? ) ds1805 toc03 wiper voltage (v) wiper resistance ( ? ) 4 3 2 1 50 100 150 200 250 300 350 0 05 v cc = 3v v cc = 5v w-l resistance vs. wiper setting ds1805 toc02 wiper setting w-l resistance (k ? ) 225 200 175 150 125 100 75 50 25 2 4 6 8 10 0 0 250 10k ? potentiometer supply current vs. temperature ds1805 toc01 temperature ( c) supply current ( a) 60 40 20 0 -20 5 10 15 20 25 30 0 -40 80 v cc = 5v v cc = 3v
ds1805 addressable digital potentiometer 6 _____________________________________________________________________ detailed description the ds1805 addressable digital potentiometer contains a single 256-position digitally controlled potentiometer. device control is achieved through a 2-wire serial inter- face. device addressing is provided through three address inputs that allow up to eight devices on a single 2-wire bus. the exact wiper position of the potentiometer can be written or read. the ds1805 is available in 16-pin so and 14-pin tssop packages. the device is available in three standard resistance values: 10k ? , 50k ? , and 100k ? . the ds1805 specified over the industrial temper- ature range. the ds1805 is provides a low-cost alterna- tive for designs based on the ds1803, but require only a single potentiometer. device operation the ds1805 is an addressable, digitally controlled device that has a single 256-position potentiometer. figure 1 shows a block diagram of the part. communication and control of the device is accom- plished through a 2-wire serial interface that has sda and sdl signals. device addressing is attained using the device chip-select inputs a0, a1, and a2. w1 scl sda a0 a1 a2 2-wire serial interface reg-0 (8-bit register) sram wiper-1 (8-bit register) command/ control unit device address selection l1 256-to-1 multiplexer potentiometer-1 h1 figure 1. functional diagram pin tssop so name function 11 h1 high end of potentiometer 23 l1 low end of potentiometer 34 w1 wiper terminal of potentiometer 6, 5, 4 7, 6, 5 a0, a1, a2 address select inputs 78 gnd ground 89 scl serial clock input 91 0 sda serial data i/o 10?3 2, 11?5 n.c. no connection 14 16 v cc 3v/5v power-supply input pin description
ds1805 addressable digital potentiometer _____________________________________________________________________ 7 the potentiometer is composed of a 256-position resis- tor array. two 8-bit registers are provided to ensure compatibility with ds1803-based designs. register-0 is a general-purpose sram byte, while register-1 is assigned to the potentiometer and is used to set the wiper position on the resistor array. the wiper terminal is multiplexed to one of 256 positions on the resistor array based on its corresponding 8-bit register value. the high- est wiper setting, ffh, is 1 lsb away from h1 (resistor 255), while the lowest setting, 00h, connects to l1. the ds1805 is a volatile device that does not maintain the position of the wiper during power-down or loss of power. on power-up, the wiper position is set to 00h (the low-end terminal). the user can then set the wiper value to a desired position. communication with the ds1805 takes place over the 2-wire serial interface consisting of the bidirectional data terminal, sda, and the serial clock input, scl. complete details of the 2-wire interface are discussed in the 2-wire serial data bus section. the 2-wire interface and address inputs a0, a1, and a2 allow operation of up to eight devices in a bus topology, with a0, a1, and a2 being the address of the device. application considerations the ds1805 is offered in three standard resistor values: 10k ? , 50k ? , and 100k ? . the resolution of the poten- tiometer is defined as r tot /256, where r tot is the total resistor value of the potentiometer. the ds1805 is designed to operate using 3v or 5v power supplies over the industrial (-40? to +85?) temperature range. maximum input signal levels across the potentiometer cannot exceed the operating power supply of the device. 2-wire serial data bus the ds1805 supports a bidirectional 2-wire bus and data transmission protocol. a device that sends data on the bus is called a transmitter, and a device receiving data is called a receiver. the device that controls the message is called a master. the devices that are con- trolled by the master are slaves. the bus must be con- trolled by a master device that generates the serial clock (scl), controls the bus access, and generates the start and stop conditions. the ds1805 operates as a slave on the 2-wire bus. connections to the bus are made through the open-drain i/o lines, sda and scl. the following bus protocol has been defined (figure 2): data transfer can be initiated only when the bus is not busy. during data transfer, the data line must remain sta- ble whenever the clock line is high. changes in the data line while the clock line is high will be interpret- ed as control signals. accordingly, the following bus conditions have been defined: bus not busy: both data and clock lines remain high. start data transfer: a change in the state of the data line from high to low while the clock is high defines a start condition. stop condition or repeated start condition repeated if more bytes are transfered ack start condition ack acknowledgement signal from receiver acknowledgement signal from receiver slave address msb scl sda r/w direction bit 12 678 9 12 89 3? figure 2. 2-wire data transfer overview
ds1805 addressable digital potentiometer 8 _____________________________________________________________________ stop data transfer: a change in the state of the data line from low to high while the clock line is high defines the stop condition. data valid: the state of the data line represents valid data when, after a start condition, the data line is sta- ble for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. figure 2 details how data transfer is accom- plished on the 2-wire bus. depending upon the state of the r/ w bit, two types of data transfer are possible. each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferred between start and stop con- ditions is not limited and is determined by the master device. the information is transferred byte-wise and each receiver acknowledges with a ninth bit. within the bus specifications a regular mode (100khz clock rate) and a fast mode (400khz clock rate) are defined. the ds1805 works in both modes. acknowledge: each receiving device, when addressed, is obliged to generate an acknowledge after the recep- tion of each byte. the master device must generate an extra clock pulse that is associated with this acknowl- edge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge-related clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generat- ing an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to gener- ate the stop condition. data transfer from a master transmitter to a slave receiver: the first byte transmitted by the master is the control byte (slave address). next follows a number of data bytes. the slave returns an acknowledge bit after each received byte. data transfer from a slave transmitter to a master receiver: the first byte (the slave address) is transmit- ted by the master. the slave then returns an acknowl- edge bit. next follows a number of data bytes transmitted by the slave to the master. the master returns an acknowledge bit after all received bytes other than the last byte. at the end of the last received byte, a ?ot acknowledge?is returned. the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repeated start condition is also the beginning of the next serial transfer, the bus will not be released. the ds1805 can operate in the following two modes: slave receiver mode: serial data and clock are received through sda and scl. after each byte is received, an acknowledge bit is transmitted. start and stop conditions are recognized as the beginning and end of a serial transfer. address recognition is performed by hardware after reception of the slave address and direction bit. slave transmitter mode: the first byte is received and handled as in the slave receiver mode. however, in this mode the direction bit will indicate that the transfer direction is reversed. serial data is transmitted on sda by the ds1805 while the serial clock is input on scl. start and stop conditions are recognized as the beginning and end of a serial transfer. slave address a control byte is the first byte received following the start condition from the master device. the control byte consists of a four-bit control code; for the ds1805, this is set as 0101 binary for read/write operations. the next three bits of the control byte are the device select bits (a2, a1, a0). they are used by the master device to select which of eight devices are to be accessed. the select bits are the three least significant bits (lsb) of the slave address. additionally, a2, a1, and a0 can be changed any time during a powered condition of the part. the last bit of the control byte (r/ w ) defines the operation to be performed. when set to a one, a read operation is selected; when set to a zero a write opera- tion is selected. figure 3 shows the control byte struc- ture for the ds1805. figure 3. control byte msb device identifier device address read/write bit 0 101a2 a1 a0 r/w lsb
ds1805 addressable digital potentiometer _____________________________________________________________________ 9 following the start condition, the ds1805 monitors the sda bus checking the device type identifier being transmitted. upon receiving the 0101 address code and appropriate device select bits, the slave device outputs an acknowledge signal on the sda line. command and protocol the ds1805? command and protocol structure of the ds1805 allows the user to read or write to both the scratchpad and potentiometer registers. figures 4 and 5 show the command structures for the part. potentiometer data values and control and command values are always transmitted most significant bit (msb) first. during communications, the receiving unit always generates the acknowledge. reading the ds1805 as shown in figure 4, the ds1805 provides one read- command operation. this operation allows the user to read both potentiometers. specifically, the r/ w bit of the control byte is set equal to a one for a read operation. communication to read the ds1805 begins with a start condition that is issued by the master device. the control byte from the master device follows the start condition. once the control byte has been received by the ds1805, the part responds with an acknowledge. the read/write bit of the control byte as stated should be set equal to one for reading the ds1805. when the master has received the acknowledge from the ds1805, the master can then begin to receive poten- tiometer wiper data. the value of the register-0 wiper position will be the first returned from the ds1805. once the eight bits of the register-0 wiper position have been transmitted, the master needs to issue an acknowledge, unless it is the only byte to be read, in which case the master issues a not acknowledge. if desired, the master can stop the communication transfer at this point by issu- ing the stop condition. however, if the value of the potentiometer-1 wiper position value is needed, commu- nication transfer can continue by clocking the remaining eight bits of the potentiometer-1 value, followed by a not acknowledge. final communication transfer is terminated by issuing the stop command. figure 4 shows the flow of the read operation. writing to the ds1805 figure 5 shows a data flow diagram for writing the ds1805. the ds1805 has three write-command opera- tions. these include write reg-0, write pot-1, and write reg-0/pot-1. the write reg-0 command allows the user to write the value of scratchpad register-0 and as an option the value of potentiometer-1. the write-1 command allows the user to write the value of potentiometer-1 only. the last write command, write-0/1, allows the user to write both registers to the same value with one command and one data value being issued. all the write operations begin with a start condition. following the start condition, the master device issues the control byte. the read/write bit of the control byte is set to zero for writing the ds1805. once the control byte has been issued and the master receives the acknowl- edgment from the ds1805, the command byte is trans- mitted to the ds1805. as mentioned above, there exist three write operations that can be used with the ds1805. figure 5 and table 1 show the binary value of each write command. figure 4. 2-wire read protocols msb start ack ack ack stop control byte lsb msb d ata byte lsb msb optional d ata byte lsb reg-0 pot-1 r/w = 1 0101a2 a1 a0 1 command command value write register-0 101010 01 write potentiometer-1 register 101010 10 write both registers 101011 11 table 1. 2-wire command words package information for the latest package outline information, go to www.maxim-ic.com/packages .
ds1805 addressable digital potentiometer maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 10 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2002 maxim integrated products printed usa is a registered trademark of maxim integrated products. figure 5. 2-wire write protocols figure 6. timing diagram ack stop msb optional d ata byte lsb pot-1 msb start ack ack ack stop control byte lsb msb command byte lsb msb d ata byte lsb pot-1 r/w = 0 msb register-0 write pot-1 write register-0 and pot-1 (same value) start ack ack ack control byte lsb msb command byte lsb msb d ata byte lsb reg-0 r/w = 0 0101a2 a1 a0 0 0101a2 a1 a0 0 0101a2 a1 a0 0 101010 01 101010 10 msb start ack ack ack stop control byte lsb msb command byte lsb msb d ata byte lsb reg-0/pot-1 value r/w = 0 101011 11 sda scl t hd:sta t low t high t r t f t buf t hd:dat t su:dat repeated start t su:sta t hd:sta t su:sto t sp stop start
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